A computing system may employ many different types of semiconductor memories communicating with a Central Processing Unit (CPU) or a memory controller through different types of buses. These memories may include volatile as well as non-volatile memories. The volatile storage may be provided by a Random Access Memory (RAM) such as, for example, one or more DRAM modules. The non-volatile storage, on the other hand, may be provided by a Solid State Drive (SSD), flash memories on Universal Serial Bus (USB) drives or on Secure Digital (SD) or microSD memory cards, and the like. The different types of buses may be part of the motherboard of the computing system, and provide physical connections to the respective memories to allow communication of relevant information—such as, for example, commands, addresses, data, and status information—throughout the system.
Typically, different Input/Output (I/O) buses generally support different data bandwidths. For example, a main memory bus or a system memory I/O bus that connects the CPU to the system memory—such as, for example, the DRAM modules—can support a significantly higher data bandwidth than that supported by another I/O bus (which also may be referred to as an “expansion bus”). The system bus supporting communication with DRAM modules may be interchangeably referred to as a “DRAM bus,” a “DRAM interface,” a “DRAM memory interface,” or a “DRAM channel.” There may be many different types of other I/O buses in a computing system. Some I/O buses include, for example, a Peripheral Component Interconnect (PCI) bus, PCI Express (PCI-E or PCIe) bus, a USB bus, a Serial Advanced Technology Attachment (SATA) bus, and so on. Generally, non-volatile storage devices may be connected to respective I/O buses. For example, a USB drive may be connected to a USB bus, and an SSD drive may be connected to a SATA bus.
It is understood that each communication bus—whether a system memory bus or another I/O bus—provides an interface that supports a specific type of communication protocol that is uniquely defined and standardized for that bus and the memories that connect to that bus. For example, the JEDEC Solid State Technology Association, formerly known as the Joint Electron Device Engineering Council (JEDEC), is an independent semiconductor engineering trade organization and standardization body that has adopted and established open standards for DRAMs such as, for example, Double Data Rate 2, 3, or 4 (DDR2/DDR3/DDR4) Synchronous DRAM (SDRAM) memories. Such standards may specify memory pinout and the memory bus interface configuration—including address and data bus configurations, as well as the communication protocol over the relevant DRAM interface such as, for example, memory reset and initialization procedures, timing requirements for various memory operations, formats of various memory command and status data, different memory read and write modes, and so on. One advantage of such standardization is that memory modules manufactured by third party vendors in compliance with the relevant standards may be used in any computing system so long as the corresponding memory buses in the computing system are designed to support the respective standardized protocols. However, on the flip side, the standardized memory interfaces may prevent a memory module designed for one type of communication bus to be installed or connected with another type of communication bus. For example, a device (e.g., a USB memory) designed to operate with a USB bus may not be connected to a SATA bus, and vice versa.